Elevated source/drain by sacrificial selective epitaxy for high performance deep submicron CMOS: Process window versus complexity

The continuous downscaling of CMOS devices aims at cost reduction and performance improvement. Process development constantly faces new constraints and integrates breakthroughs to overcome them. In deep submicron CMOS generations, scalability is in part limited by conflicting needs for shallow silicided junctions and low junction leakage. Both requirements can be met using elevated source/drain (/sup E/S/D) architecture. Although this solution has long been established, its avoidable extra complexity has delayed its introduction in industrial mainstream technologies. However, as device scaling continues, process windows are reducing critically. As a result, /sup E/S/D architecture is attracting a growing interest. This paper reports on a 0.18 /spl mu/m CMOS technology featuring /sup E/S/D made with sacrificial selective epitaxy. This technology is examined from the standpoints of manufacturability and performance improvement. In contrast to most /sup E/S/D approaches, the selective epitaxy is done after junction formation, resulting in increased process window. Our /sup E/S/D process leads to dc and rf device performance enhancements. Nevertheless, the same functionality gains were achieved by a fine-tuning of the reference conventional low-cost process. Process window reduction will require /sup E/S/D for generations below 0.13 /spl mu/m.