Limitation of CMOS supply-voltage scaling by MOSFET threshold-voltage variation

A fundamental limit of CMOS supply-voltage (V/sub cc/) scaling has been investigated and quantified as a function of the statistical variation of MOSFET threshold-voltage (V/sub T/). Based on the data extracted from a sub 0.5 /spl mu/m logic technology, the variation of ring-oscillator propagation-delay (T/sub d/) significantly increases as V/sub cc/ is scaled down towards the MOSFET V/sub T/. An empirical power-law relationship was then derived to describe the scattering of circuit speed (/spl Delta/T/sub pd/) as a function of MOSFET V/sub T/ variation (/spl Delta/V/sub T/) and (V/sub cc/-V/sub T/). Agreement between the model and the experimental data was established for V/sub cc/ values from 4.0 to 0.9 V. This fundamental limit of CMOS V/sub cc/, scaling poses an additional challenge for the design and manufacturing of high-performance, low-power portable systems and battery-based equipment.< >