Solution-based Fabrication of High-K Gate Dielectrics for Next-Generation Metal-Oxide Semiconductor Transistors

The semiconductor industry is currently in the process of a transition from 200 mm to 300 mm wafer size and is facing high manufacturing costs and enhanced energy consumption. It is believed the associated retooling of processing equipment capable of handling 300 mm wafers and requirements for innovative materials, will become the most expensive in the history of the industry. This situation accelerates the development of semiconductor processes that use simpler apparatus and are more flexible, in order to reduce the manufacturing cost to a manageable level. At the same time, downscaling of the metal-oxide semiconductor (MOS) device to the sub-0.1 mum regime poses serious problems, because conventional SiO2 gate dielectrics would become thinner than 2.0 nm, giving a large leakage current of 1 A cm-2 due to quantum tunneling, and causing unsupportably large energy consumption and lessened device reliability. Since tunneling decreases exponentially with increasing thickness, the tunneling leak current can be reduced by using thicker films with dielectric constants higher than that of SiO2: the equivalent capacitance or equivalent SiO2 thickness (EOT). There exists strong motivation for development of alternate, high-dielectric-constant (high-K) metal oxide gate dielectrics as a replacement for low-k SiO2.