A low-power PLA for a signal processor

A low-power PLA for a signal processor

A standard fast programmable logic array (PLA) structure is discussed, with emphasis on its power consumption drawbacks. An exploration of alternatives to this structure leads to a presentation of the architecture and design of a low-power PLA structure used in a digital signal processing (DSP) envi...

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Veröffentlicht in:IEEE journal of solid-state circuits 1991-02, Vol.26 (2), p.107-115
1. Verfasser: Linz, A.R.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithms
CMOS technology
Codecs
Digital signal processing
Energy consumption
Filters
Power dissipation
Programmable logic arrays
Signal design
Signal processing
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Beschreibung
Zusammenfassung:A standard fast programmable logic array (PLA) structure is discussed, with emphasis on its power consumption drawbacks. An exploration of alternatives to this structure leads to a presentation of the architecture and design of a low-power PLA structure used in a digital signal processing (DSP) environment. This PLA achieves low power consumption by a combination of pipelining, use of a NAND-OR configuration, and a simplified addressing scheme. Experimental results for the temperature range of 0 to 70 degrees C indicate that the circuit works as expected in a range extending to at least 3.5 V.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.68124