A low-inductance, low-I(c) HTS junction process

One of the challenges In fabricating digital circuitry with high temperature superconductors (HTS) is in developing a reliable junction process. The requirements of this junction process include: low-parasitic inductance, well-targeted and reproducible total inductance, uniformity in I(c) and R(n), and also well-targeted I(c) and I(c)R(n) product greater than 300 muV at 65 K. Junction inductance can be greatly reduced by fabrication above a groundplane. Yet the addition of a groundplane introduces fabrication issues such as film smoothness and maintenance of epitaxy through the multiple layers necessary. Step-edge junctions and SNS edge junctions with groundplanes are examined and compared through a Taguchi experimental design series. Process equipment modifications in our HTS foundry necessary to reach our fabrication goals are outlined