A leakage current mechanism caused by the interaction of residual oxidation stress and high-energy ion implantation impact in advanced CMOS technology

In this paper, we report abnormal junction leakage current characteristics in sub-quarter micron CMOS formed by OSELO-II isolation method and high-energy ion implantation for well formation. The phenomena have not been found in other isolation schemes such as single Si/sub 3/N/sub 4/ spacer OSELO (SSS-OSELO), modified conventional LOCOS (MLOCOS) and shallow trench isolation (STI). From the defect analysis and process simulation based on the actual recipe, the abnormal leakage is found to be generated from the lattice defects at the edge of field oxide and caused by the combination of oxidation stress, and high-energy ion implantation. A process condition in the high-energy ion implantation and isolation process is proposed to reduce the leakage current.