A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set

A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set

A 12:1 multiplexer and 11:2 demultiplexer that operate at up to 3 Gb/s are discussed. The circuits were fabricated with a 1- mu m-design-rule silicon NMOS VLSI technology and operate from a 3.5-V power supply. The multiplexer chip has 200 gates and dissipates 0.5 W of power. The demultiplexer chip h...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE journal of solid-state circuits 1989-06, Vol.24 (3), p.814-821
Hauptverfasser: Bayruns, R.J., Hofstatter, E.A., Weston, H.T.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Clocks
Counting circuits
Electronics
Exact sciences and technology
Gallium arsenide
Integrated circuits
Integrated circuits by function (including memories and processors)
Latches
Logic circuits
MOS devices
Multiplexing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Shift registers
Silicon
Very large scale integration
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A 12:1 multiplexer and 11:2 demultiplexer that operate at up to 3 Gb/s are discussed. The circuits were fabricated with a 1- mu m-design-rule silicon NMOS VLSI technology and operate from a 3.5-V power supply. The multiplexer chip has 200 gates and dissipates 0.5 W of power. The demultiplexer chip has 400 gates and dissipates 0.75 W. Performance of these devices compares well in both speed and power to the best gallium-arsenide results reported to date.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.32044