Hardware implementation of Montgomery's modular multiplication algorithm
Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in s...
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| Veröffentlicht in: | IEEE transactions on computers 1993-06, Vol.42 (6), p.693-699 |
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| container_end_page | 699 |
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| container_title | IEEE transactions on computers |
| container_volume | 42 |
| creator | Eldridge, S.E. Walter, C.D. |
| description | Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic.< > |
| doi_str_mv | 10.1109/12.277287 |
| format | Article |
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Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic.< ></description><subject>Algorithmics. Computability. Computer arithmetics</subject><subject>Applied sciences</subject><subject>Circuits</subject><subject>Clocks</subject><subject>Computer architecture</subject><subject>Computer science; control theory; systems</subject><subject>Cryptography</subject><subject>Digital arithmetic</subject><subject>Exact sciences and technology</subject><subject>Hardware</subject><subject>Logic</subject><subject>Public key</subject><subject>Security</subject><subject>Theoretical computing</subject><issn>0018-9340</issn><issn>1557-9956</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNqNkD1PwzAQQC0EEqUwsDJlQCCGFH8ksW9EFVCkIhaYI8d2ipEdBzsR6r-nVSpmphvu3TvpIXRJ8IIQDPeELijnVPAjNCNlyXOAsjpGM4yJyIEV-BSdpfSFMa4ohhlarWTUPzKazPreGW-6QQ42dFlos9fQDZvgTdzepswHPToZMz-6wfbOqgmTbhOiHT79OTpppUvm4jDn6OPp8X25ytdvzy_Lh3WuGBFDLoEzTgQzLZRaGaJZq0mFKWijCi2pKpkADYI1VGAoSNGoCnMFRjQNlxLYHN1M3j6G79GkofY2KeOc7EwYU00FFQKKf4DVLgEryQ68m0AVQ0rRtHUfrZdxWxNc76PWhNZT1B17fZDKpKRro-yUTX8HDAQw2P--mjBrjPnbHhy_8-t_LQ</recordid><startdate>19930601</startdate><enddate>19930601</enddate><creator>Eldridge, S.E.</creator><creator>Walter, C.D.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19930601</creationdate><title>Hardware implementation of Montgomery's modular multiplication algorithm</title><author>Eldridge, S.E. ; Walter, C.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c318t-a9737183ef95dce1d3fd16029dec4da2c5389d983b2809414bc607c9e8bb7aa93</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Algorithmics. Computability. Computer arithmetics</topic><topic>Applied sciences</topic><topic>Circuits</topic><topic>Clocks</topic><topic>Computer architecture</topic><topic>Computer science; control theory; systems</topic><topic>Cryptography</topic><topic>Digital arithmetic</topic><topic>Exact sciences and technology</topic><topic>Hardware</topic><topic>Logic</topic><topic>Public key</topic><topic>Security</topic><topic>Theoretical computing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Eldridge, S.E.</creatorcontrib><creatorcontrib>Walter, C.D.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Eldridge, S.E.</au><au>Walter, C.D.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Hardware implementation of Montgomery's modular multiplication algorithm</atitle><jtitle>IEEE transactions on computers</jtitle><stitle>TC</stitle><date>1993-06-01</date><risdate>1993</risdate><volume>42</volume><issue>6</issue><spage>693</spage><epage>699</epage><pages>693-699</pages><issn>0018-9340</issn><eissn>1557-9956</eissn><coden>ITCOB4</coden><abstract>Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/12.277287</doi><tpages>7</tpages></addata></record> |
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| ispartof | IEEE transactions on computers, 1993-06, Vol.42 (6), p.693-699 |
| issn | 0018-9340 1557-9956 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithmics. Computability. Computer arithmetics Applied sciences Circuits Clocks Computer architecture Computer science control theory systems Cryptography Digital arithmetic Exact sciences and technology Hardware Logic Public key Security Theoretical computing |
| title | Hardware implementation of Montgomery's modular multiplication algorithm |
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