Hardware implementation of Montgomery's modular multiplication algorithm

Hardware implementation of Montgomery's modular multiplication algorithm

Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in s...

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Veröffentlicht in:IEEE transactions on computers 1993-06, Vol.42 (6), p.693-699
Hauptverfasser: Eldridge, S.E., Walter, C.D.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithmics. Computability. Computer arithmetics
Applied sciences
Circuits
Clocks
Computer architecture
Computer science
control theory
systems
Cryptography
Digital arithmetic
Exact sciences and technology
Hardware
Logic
Public key
Security
Theoretical computing
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Zusammenfassung:Hardware is described for implementing the fast modular multiplication algorithm developed by P.L. Montgomery (1985). Comparison with previous techniques shows that this algorithm is up to twice as fast as the best currently available and is more suitable for alternative architectures. The gain in speed arises from the faster clock that results from simpler combinational logic.< >
ISSN:0018-9340
1557-9956
DOI:10.1109/12.277287