An algorithmic A/D switched-current converter for smart signal digitization with self-test features

Practical aspects of the implementation of test circuitry into CMOS design of an analog-to-digital (A/D) converter are discussed. Focus is placed on a design-for-test in switched-current mode circuitry. As an example, analysis of an A/D converter designed in switched-current technique is used for data sampling. The problems concerned with controllability and observability of internal and, are discussed. A pipelined switched-current A/D converter designed in 0.6-micron CMOS technology is described. Current mode enables operation down to 3 V thus is suitable for battery-powered applications. The system integrates band-gap reference and independent supervisory circuit with 1% accuracy. Current consumption in sleep mode is less than 1 microamp. A/D converter is prepared to meet 1452.2 specifications. The models were used to verify theoretical proposals by means of SPICE simulations.