Design of a low-power 32 K CMOS programmable delay-line memory

Design of a low-power 32 K CMOS programmable delay-line memory

A design of a programmable digital delay based on shift registers in 1.2- mu m CMOS technology is presented. The main features of this design are 20-MHz operating frequency and 200-mW power dissipation for four 1025-pixel*8-b delay lines. An integrable circuit technique for decreasing the power diss...

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Veröffentlicht in:IEEE journal of solid-state circuits 1990-02, Vol.25 (1), p.234-238
Hauptverfasser: Dejhan, K., Demassieux, N., Colavin, O., Galisson, A., Artieri, A., Jutand, F.
Format: Artikel
Sprache:eng
Schlagworte:
Circuits
CMOS technology
Delay lines
Frequency conversion
Image sampling
Power dissipation
Random access memory
Read-write memory
Shift registers
Strontium
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Zusammenfassung:A design of a programmable digital delay based on shift registers in 1.2- mu m CMOS technology is presented. The main features of this design are 20-MHz operating frequency and 200-mW power dissipation for four 1025-pixel*8-b delay lines. An integrable circuit technique for decreasing the power dissipation of the shift register is also suggested.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.50309