Distributed arithmetic implementation of artificial neural networks

A brief overview of the computational requirements and some hardware developments for backpropagation networks is presented. The basic distributed arithmetic approach as it is used in digital filter implementations is discussed. A hardware neural network, the design of which is based on distributed arithmetic, is described. The proposed formal neuron has a regular circuit pattern as it consists mostly of memory hardware. Thus a wafer scale implementation of a network composed of such neurons may provide a cost effective way to solve many real-time pattern recognition problems.< >