Development of a radiation tolerant 1M SRAM on fully-depleted SOI

Development of a radiation tolerant 1M SRAM on fully-depleted SOI

1M SRAMs were fabricated on fully-depleted SOI using 0.5 um design rules. The SRAMs were evaluated for speed/power, prompt dose upset, SEE, and total dose hardness. As compared to the identical design fabricated on bulk CMOS, improved results were seen for performance and prompt dose hardness. On th...

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Veröffentlicht in:IEEE Transactions on Nuclear Science 1998-12, Vol.45 (6), p.2436-2441
Hauptverfasser: Brady, F.T., Brown, R., Rockett, L., Vasquez, J.
Format: Artikel
Sprache:eng
Schlagworte:
Circuits
CMOS process
CMOS technology
DESIGN
Design optimization
Dielectric substrates
Doping
ERRORS
INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS
PHYSICAL RADIATION EFFECTS
Radiation hardening
Random access memory
SEMICONDUCTOR STORAGE DEVICES
Silicon
Single event upset
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Beschreibung
Zusammenfassung:1M SRAMs were fabricated on fully-depleted SOI using 0.5 um design rules. The SRAMs were evaluated for speed/power, prompt dose upset, SEE, and total dose hardness. As compared to the identical design fabricated on bulk CMOS, improved results were seen for performance and prompt dose hardness. On the other hand, a low n-channel snapback voltage degraded the standby leakage, total dose hardness, and SEU hardness. The total dose hardness was expectedly low since no attempt was made to harden the buried oxide for this evaluation. This effort reflects the most complicated circuit reported on fully-depleted SOI.
ISSN:0018-9499
1558-1578
DOI:10.1109/23.736483