Compiler-directed scratch pad memory optimization for embedded multiprocessors

This paper presents a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets at reducing extra off-chip memory accesses caused by interprocessor communication...

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Veröffentlicht in:IEEE transactions on very large scale integration (VLSI) systems 2004-03, Vol.12 (3), p.281-287
Hauptverfasser: Kandemir, M., Kadayif, I., Choudhary, A., Ramanujam, J., Kolcu, I.
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Sprache:eng
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Zusammenfassung:This paper presents a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we propose an optimization algorithm that targets at reducing extra off-chip memory accesses caused by interprocessor communication. This is achieved by increasing the application-wide reuse of data that resides in scratch-pad memories of processors. Our results obtained using four array-intensive image processing applications indicate that exploiting interprocessor data sharing can reduce energy-delay product significantly on a four-processor embedded system.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2004.824299