Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices

Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices

This paper presents a flexible filter and control unit structure for implementing different VLSI architectures on two-dimensional DWT. These structures are applied over three different architectures: a direct approach, Recursive Pyramidal Algorithm (RPA) architecture, and a new proposed modification...

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Veröffentlicht in:Microprocessors and microsystems 2004-11, Vol.28 (9), p.509-518
Hauptverfasser: Colom-Palero, Ricardo José, Gadea-Girones, Rafael, Ballester-Merelo, Francisco José, Martı́nez-Peiro, Marcos
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Sprache:eng
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Image processing
Programmable logic device
Signal processing
VLSI design
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container_end_page 518
container_issue 9
container_start_page 509
container_title Microprocessors and microsystems
container_volume 28
creator Colom-Palero, Ricardo José
Gadea-Girones, Rafael
Ballester-Merelo, Francisco José
Martı́nez-Peiro, Marcos
description This paper presents a flexible filter and control unit structure for implementing different VLSI architectures on two-dimensional DWT. These structures are applied over three different architectures: a direct approach, Recursive Pyramidal Algorithm (RPA) architecture, and a new proposed modification of RPA. This modified architecture works in a non-separable fashion using a parallel filter structure with distributed control to compute all the DWT resolution levels. It is fully modular and scalable, with low latency and high throughput performance. Implementation results based on a Virtex-II FPGA device are included. Real-time video processing is achieved.
doi_str_mv 10.1016/j.micpro.2004.05.003
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subjects Image processing
Programmable logic device
Signal processing
VLSI design
title Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices
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