Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices

This paper presents a flexible filter and control unit structure for implementing different VLSI architectures on two-dimensional DWT. These structures are applied over three different architectures: a direct approach, Recursive Pyramidal Algorithm (RPA) architecture, and a new proposed modification of RPA. This modified architecture works in a non-separable fashion using a parallel filter structure with distributed control to compute all the DWT resolution levels. It is fully modular and scalable, with low latency and high throughput performance. Implementation results based on a Virtex-II FPGA device are included. Real-time video processing is achieved.