COD: alternative architectures for high speed packet switching

Architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to utilize advances in photonic technology to enable higher speeds. The authors introduce cascaded optical delay line (COD) architectures. The COD architectures utilize an extremely simple distributed electronic control algorithm to configure the states of 2/spl times/2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessary. The simplicity of the architectures may also make them suitable for "lightweight" all-electronic implementations. For optical implementations, the number of 2/spl times/2 photonic switches used is a significant factor determining cost. The authors present a "baseline" architecture for a 2/spl times/2 buffered packet switch that is work conserving and has the first-in, first-out (FIFO) property. If the arrival processes are independent and without memory, the maximum utilization factor is /spl rho/, and the maximum acceptable packet loss probability is /spl epsiv/, then the required number of 2/spl times/2 photonic switches is O(log(/spl epsiv/)/log(/spl gamma/)), where /spl gamma/=/spl rho//sup 2//(/spl rho//sup 2/+4-4/spl rho/). If one modifies the baseline architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2/spl times/2 photonic switches is reduced to O(log[log(/spl epsiv/)/log(/spl gamma/)]). The required number of 2/spl times/2 photonic switches is essentially insensitive to the distribution of packet arrivals, but long delay lines are required for bursty traffic.