A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo

A fully integrated partial response maximum likelihood (PRML) read/write IC with analog adaptive equalization operates up to 200 MSample/s. The chip implements both matched spectral null (MSN) trellis and standard PR4 Viterbi detectors in the digital domain as well as digital servo. The device is in...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1997-11, Vol.32 (11), p.1824-1838
Hauptverfasser:	Alini, R., Betti, G., Bietti, I., Bollati, G., Brianti, F., Dati, A., Demicheli, M., Gadducci, P., Marchese, S., Marconetti, E., Pisati, V., Zuffada, M., Castello, R., Heydari, F., Gillen, P., Maguire, G., Marrow, M., McDonagh, S., O'Brien, F., O'Brien, J., O'hEarcain, N., Reddy, D., Fredrickson, L., Stone, D., Volz, L.
Format:	Artikel
Sprache:	eng
Schlagworte:	Adaptive equalizers Analog integrated circuits BiCMOS integrated circuits Detectors Digital integrated circuits Digital signal processing chips Maximum likelihood detection Microelectronics Servomechanisms Viterbi algorithm
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Beschreibung
Zusammenfassung:	A fully integrated partial response maximum likelihood (PRML) read/write IC with analog adaptive equalization operates up to 200 MSample/s. The chip implements both matched spectral null (MSN) trellis and standard PR4 Viterbi detectors in the digital domain as well as digital servo. The device is integrated in a mature 0.7-/spl mu/m BiCMOS technology, has a die size of 54 mm/sup 2/, and dissipates 2 W with MSN code or 1.5 W with PR4 code at 4.5-V supply and 200 MSample/s.
ISSN:	0018-9200 1558-173X
DOI:	10.1109/4.641707