A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier
An 8-Mb (1-Mwords*8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7- mu m n-well CMOS, double-...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1990-02, Vol.25 (1), p.30-35 |
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| container_end_page | 35 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 25 |
| creator | Kotani, H. Akamatsu, H. Matsushima, J. Okada, S. Shiragasawa, T. Yamada, T. Inoue, M. |
| description | An 8-Mb (1-Mwords*8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7- mu m n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8*3.0 mu m/sup 2/, and the chip area is 12.7*16.91 mm/sup 2/.< > |
| doi_str_mv | 10.1109/4.50280 |
| format | Article |
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The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7- mu m n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8*3.0 mu m/sup 2/, and the chip area is 12.7*16.91 mm/sup 2/.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.50280</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit noise ; Counting circuits ; Current supplies ; DRAM chips ; HDTV ; Noise generators ; Power supplies ; Random access memory ; Read-write memory</subject><ispartof>IEEE journal of solid-state circuits, 1990-02, Vol.25 (1), p.30-35</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c272t-2d40edd83a4ac36c8013194ef0483fb5f039890db9ca58712d2f61055cdd8a473</citedby><cites>FETCH-LOGICAL-c272t-2d40edd83a4ac36c8013194ef0483fb5f039890db9ca58712d2f61055cdd8a473</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/50280$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27915,27916,54749</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/50280$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kotani, H.</creatorcontrib><creatorcontrib>Akamatsu, H.</creatorcontrib><creatorcontrib>Matsushima, J.</creatorcontrib><creatorcontrib>Okada, S.</creatorcontrib><creatorcontrib>Shiragasawa, T.</creatorcontrib><creatorcontrib>Yamada, T.</creatorcontrib><creatorcontrib>Inoue, M.</creatorcontrib><title>A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>An 8-Mb (1-Mwords*8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. 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The cell size is 1.8*3.0 mu m/sup 2/, and the chip area is 12.7*16.91 mm/sup 2/.< ></description><subject>Circuit noise</subject><subject>Counting circuits</subject><subject>Current supplies</subject><subject>DRAM chips</subject><subject>HDTV</subject><subject>Noise generators</subject><subject>Power supplies</subject><subject>Random access memory</subject><subject>Read-write memory</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1990</creationdate><recordtype>article</recordtype><recordid>eNo9kM1LAzEQxYMoWKt49paTnlInX7vZYym2FVoEUfC2pMksRna7NdlW9K93dcXTzPB-8-A9Qi45TDiH4lZNNAgDR2TEtTaM5_LlmIwAuGGFADglZym99adSho_IYko1sPXyixq23oSOHoLHlj5O1_QjdK_UUtfW-2ZLfYjoutD2WwwHpAm3CaltdnWoAsZzclLZOuHF3xyT5_nd02zJVg-L-9l0xZzIRceEV4DeG2mVdTJzBrjkhcIKlJHVRlcgC1OA3xTOapNz4UWVcdDa9U9W5XJMrgffXWzf95i6sgnJYV3bLbb7VArTB1ZZ1oM3A-him1LEqtzF0Nj4WXIof4oqVflbVE9eDWRAxH9q0L4B_ohgGQ</recordid><startdate>19900201</startdate><enddate>19900201</enddate><creator>Kotani, H.</creator><creator>Akamatsu, H.</creator><creator>Matsushima, J.</creator><creator>Okada, S.</creator><creator>Shiragasawa, T.</creator><creator>Yamada, T.</creator><creator>Inoue, M.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19900201</creationdate><title>A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier</title><author>Kotani, H. ; Akamatsu, H. ; Matsushima, J. ; Okada, S. ; Shiragasawa, T. ; Yamada, T. ; Inoue, M.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c272t-2d40edd83a4ac36c8013194ef0483fb5f039890db9ca58712d2f61055cdd8a473</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Circuit noise</topic><topic>Counting circuits</topic><topic>Current supplies</topic><topic>DRAM chips</topic><topic>HDTV</topic><topic>Noise generators</topic><topic>Power supplies</topic><topic>Random access memory</topic><topic>Read-write memory</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kotani, H.</creatorcontrib><creatorcontrib>Akamatsu, H.</creatorcontrib><creatorcontrib>Matsushima, J.</creatorcontrib><creatorcontrib>Okada, S.</creatorcontrib><creatorcontrib>Shiragasawa, T.</creatorcontrib><creatorcontrib>Yamada, T.</creatorcontrib><creatorcontrib>Inoue, M.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kotani, H.</au><au>Akamatsu, H.</au><au>Matsushima, J.</au><au>Okada, S.</au><au>Shiragasawa, T.</au><au>Yamada, T.</au><au>Inoue, M.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1990-02-01</date><risdate>1990</risdate><volume>25</volume><issue>1</issue><spage>30</spage><epage>35</epage><pages>30-35</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>An 8-Mb (1-Mwords*8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and is fabricated with a 0.7- mu m n-well CMOS, double-level polysilicon, single-polycide, and double-level metal technology. The memory cell is a surrounding hi-capacitance cell structure. The cell size is 1.8*3.0 mu m/sup 2/, and the chip area is 12.7*16.91 mm/sup 2/.< ></abstract><pub>IEEE</pub><doi>10.1109/4.50280</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1990-02, Vol.25 (1), p.30-35 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_28173466 |
| source | IEEE Electronic Library (IEL) |
| subjects | Circuit noise Counting circuits Current supplies DRAM chips HDTV Noise generators Power supplies Random access memory Read-write memory |
| title | A 50-MHz 8-Mbit video RAM with a column direction drive sense amplifier |
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