A 21-mW 8-b 125-MSample/s ADC in 0.09-mm(2) 0.13-mum CMOS

A 21-mW 8-b 125-MSample/s ADC in 0.09-mm(2) 0.13-mum CMOS

This paper presents an 8-b two-step subranging analog-to-digital (ADC) using interpolation, averaging, offset compensation, and pipelining techniques to accomplish an effective number of bits of 7.6 b at 125 MSample/s. The 0.13-mum CMOS ADC occupies 0.09 mm(2) and consumes 21 mW.

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Veröffentlicht in:IEEE journal of solid-state circuits 2004-12, Vol.39 (12), p.2116-2125
Hauptverfasser: Mulder, J, Ward, C M, Lin, Chi-Hung, Kruse, D, Westra, J R, Lugthart, M, Arslan, E, van de Plassche, R J, Bult, K, van der Goes, F M L
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Sprache:eng
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Zusammenfassung:This paper presents an 8-b two-step subranging analog-to-digital (ADC) using interpolation, averaging, offset compensation, and pipelining techniques to accomplish an effective number of bits of 7.6 b at 125 MSample/s. The 0.13-mum CMOS ADC occupies 0.09 mm(2) and consumes 21 mW.
ISSN:0018-9200
DOI:10.1109/JSSC.2004.836235