Fabrication of N+/P ultra-shallow junctions by plasma doping for 65 nm CMOS technology

As semiconductor devices keep shrinking in size, the fabrication of ultra-shallow junctions (USJ) is becoming a key issue for future CMOS technologies. In this study, we propose for the first time to demonstrate and extensively characterize the capability of plasma doping (PLAD) for fabricating *h-type USJ. P-type silicon wafers were used and doped by plasma using AsH3/Xe or AsF5 as precursors. We have performed a Design Of Experiment (DOE) study with AsF5 implants to model the junction characteristics (junction depth Xj, sheet resistance Rs). Through a direct comparison with standard As+ ultra-low energy implants, AsF5 and AsH3 plasma-doped wafers show a significant improvement of the junctions characteristics. By optimizing each process parameter, we clearly demonstrate the ability of PLAD to fabricate, with a conventional annealing method, the N+/P ultra-shallow junctions required for the NMOS transistors of the future 65 nm CMOS technology.