A 660 MB/s interface megacell portable circuit in 0.3 mu m-0.7mu m CMOS ASIC

A 660 MB/s interface megacell portable circuit in 0.3 mu m-0.7mu m CMOS ASIC

A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 mum to 0.3 mum. The chip is 0.9x3.4 mm(2)...

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Veröffentlicht in:IEEE journal of solid-state circuits 1996-12, Vol.31 (12), p.1995-2003
Hauptverfasser: Donnelly, K S, Chan, Yiu-Fai, Ho, J T C, Tran, Chanh V, Patel, S, Lau, Benedict, Kim, Jun, Chau, Pak Shing, Huang, C, Wei, J, Yu, Leung, Tarver, R, Kulkami, R, Stark, D, Johnson, M G
Format: Artikel
Sprache:eng
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Zusammenfassung:A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 mum to 0.3 mum. The chip is 0.9x3.4 mm(2) using 0.3 mum rules
ISSN:0018-9200
DOI:10.1109/4.545823