A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC

A set of power minimization techniques is proposed for pipelined ADC's. These techniques include commutating feedback-capacitors, sharing of the op-amp between the adjacent stages of the pipeline, reusing the first stage of the op-amp as comparator pre-amp, and exploiting parasitic capacitors for common-mode feedback. This set of low-power design techniques is incorporated in an experimental chip fabricated in a 1.2-/spl mu/m, double-poly, double-metal CMOS process. At 12-b 5-Msample/s, the chip dissipates 33 mW of power from a 2.5-V analog supply while achieving a maximum differential nonlinearity (DNL) of -0.78 and +0.63 least-significant bits (LSB) with a peak signal-to-noise ratio (SNR) of 67.6 dB.