A 1-V TFT-load SRAM using a two-step word-voltage method
A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a two-step word-voltage (TSW) method, a submicroampere boosted-level generator using a multivibrator, and a sense amplifier using low-threshold MOSFETs. An access time of 250 ns and a standby cur...
Gespeichert in:
Veröffentlicht in: | IEEE journal of solid-state circuits 1992-11, Vol.27 (11), p.1519-1524 |
---|---|
Hauptverfasser: | , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 1524 |
---|---|
container_issue | 11 |
container_start_page | 1519 |
container_title | IEEE journal of solid-state circuits |
container_volume | 27 |
creator | Ishibashi, K. Takasugi, K. Hashimoto, T. Sasaki, K. |
description | A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a two-step word-voltage (TSW) method, a submicroampere boosted-level generator using a multivibrator, and a sense amplifier using low-threshold MOSFETs. An access time of 250 ns and a standby current of 0.23 mu A were achieved for a 4-kb test chip using a 10.2- mu m/sup 2/ TFT-load cell. This technology is applicable for high-density and single-battery operational SRAMS.< > |
doi_str_mv | 10.1109/4.165331 |
format | Article |
fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28146561</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>165331</ieee_id><sourcerecordid>28146561</sourcerecordid><originalsourceid>FETCH-LOGICAL-c221t-8d754b3152627865c0c337b70903cf162c0127a2951e41ab4c733400fe539db23</originalsourceid><addsrcrecordid>eNqN0EtLAzEUBeAgCtYquHaVlbhJzc07y1KsChVBq7gLmUymjkybOpm2-O-tjODW1eFyPu7iIHQOdARA7bUYgZKcwwEagJSGgOZvh2hAKRhiGaXH6CTnj_0phIEBMmMM5BXPp3PSJF_i56fxA97kerXAHne7RHIX13iX2pJsU9P5RcTL2L2n8hQdVb7J8ew3h-hlejOf3JHZ4-39ZDwjgTHoiCm1FAUHyRTTRslAA-e60NRSHipQLFBg2jMrIQrwhQiac0FpFSW3ZcH4EF32f9dt-tzE3LllnUNsGr-KaZMdM8Yqq8U_IAglFezhVQ9Dm3JuY-XWbb307ZcD6n42dML1G-7pRU_rGOMf68tvjQdnUg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28146561</pqid></control><display><type>article</type><title>A 1-V TFT-load SRAM using a two-step word-voltage method</title><source>IEEE</source><creator>Ishibashi, K. ; Takasugi, K. ; Hashimoto, T. ; Sasaki, K.</creator><creatorcontrib>Ishibashi, K. ; Takasugi, K. ; Hashimoto, T. ; Sasaki, K.</creatorcontrib><description>A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a two-step word-voltage (TSW) method, a submicroampere boosted-level generator using a multivibrator, and a sense amplifier using low-threshold MOSFETs. An access time of 250 ns and a standby current of 0.23 mu A were achieved for a 4-kb test chip using a 10.2- mu m/sup 2/ TFT-load cell. This technology is applicable for high-density and single-battery operational SRAMS.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.165331</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Batteries ; Circuit testing ; CMOS technology ; Electronic equipment ; Low voltage ; MOSFET circuits ; Operational amplifiers ; Random access memory ; Thin film transistors ; Threshold voltage</subject><ispartof>IEEE journal of solid-state circuits, 1992-11, Vol.27 (11), p.1519-1524</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c221t-8d754b3152627865c0c337b70903cf162c0127a2951e41ab4c733400fe539db23</citedby><cites>FETCH-LOGICAL-c221t-8d754b3152627865c0c337b70903cf162c0127a2951e41ab4c733400fe539db23</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/165331$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/165331$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Ishibashi, K.</creatorcontrib><creatorcontrib>Takasugi, K.</creatorcontrib><creatorcontrib>Hashimoto, T.</creatorcontrib><creatorcontrib>Sasaki, K.</creatorcontrib><title>A 1-V TFT-load SRAM using a two-step word-voltage method</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a two-step word-voltage (TSW) method, a submicroampere boosted-level generator using a multivibrator, and a sense amplifier using low-threshold MOSFETs. An access time of 250 ns and a standby current of 0.23 mu A were achieved for a 4-kb test chip using a 10.2- mu m/sup 2/ TFT-load cell. This technology is applicable for high-density and single-battery operational SRAMS.< ></description><subject>Batteries</subject><subject>Circuit testing</subject><subject>CMOS technology</subject><subject>Electronic equipment</subject><subject>Low voltage</subject><subject>MOSFET circuits</subject><subject>Operational amplifiers</subject><subject>Random access memory</subject><subject>Thin film transistors</subject><subject>Threshold voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1992</creationdate><recordtype>article</recordtype><recordid>eNqN0EtLAzEUBeAgCtYquHaVlbhJzc07y1KsChVBq7gLmUymjkybOpm2-O-tjODW1eFyPu7iIHQOdARA7bUYgZKcwwEagJSGgOZvh2hAKRhiGaXH6CTnj_0phIEBMmMM5BXPp3PSJF_i56fxA97kerXAHne7RHIX13iX2pJsU9P5RcTL2L2n8hQdVb7J8ew3h-hlejOf3JHZ4-39ZDwjgTHoiCm1FAUHyRTTRslAA-e60NRSHipQLFBg2jMrIQrwhQiac0FpFSW3ZcH4EF32f9dt-tzE3LllnUNsGr-KaZMdM8Yqq8U_IAglFezhVQ9Dm3JuY-XWbb307ZcD6n42dML1G-7pRU_rGOMf68tvjQdnUg</recordid><startdate>19921101</startdate><enddate>19921101</enddate><creator>Ishibashi, K.</creator><creator>Takasugi, K.</creator><creator>Hashimoto, T.</creator><creator>Sasaki, K.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope></search><sort><creationdate>19921101</creationdate><title>A 1-V TFT-load SRAM using a two-step word-voltage method</title><author>Ishibashi, K. ; Takasugi, K. ; Hashimoto, T. ; Sasaki, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c221t-8d754b3152627865c0c337b70903cf162c0127a2951e41ab4c733400fe539db23</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1992</creationdate><topic>Batteries</topic><topic>Circuit testing</topic><topic>CMOS technology</topic><topic>Electronic equipment</topic><topic>Low voltage</topic><topic>MOSFET circuits</topic><topic>Operational amplifiers</topic><topic>Random access memory</topic><topic>Thin film transistors</topic><topic>Threshold voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Ishibashi, K.</creatorcontrib><creatorcontrib>Takasugi, K.</creatorcontrib><creatorcontrib>Hashimoto, T.</creatorcontrib><creatorcontrib>Sasaki, K.</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ishibashi, K.</au><au>Takasugi, K.</au><au>Hashimoto, T.</au><au>Sasaki, K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 1-V TFT-load SRAM using a two-step word-voltage method</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1992-11-01</date><risdate>1992</risdate><volume>27</volume><issue>11</issue><spage>1519</spage><epage>1524</epage><pages>1519-1524</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A 1-V SRAM using a TFT load cell was developed. Key circuits for obtaining the low-voltage operation are a two-step word-voltage (TSW) method, a submicroampere boosted-level generator using a multivibrator, and a sense amplifier using low-threshold MOSFETs. An access time of 250 ns and a standby current of 0.23 mu A were achieved for a 4-kb test chip using a 10.2- mu m/sup 2/ TFT-load cell. This technology is applicable for high-density and single-battery operational SRAMS.< ></abstract><pub>IEEE</pub><doi>10.1109/4.165331</doi><tpages>6</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0018-9200 |
ispartof | IEEE journal of solid-state circuits, 1992-11, Vol.27 (11), p.1519-1524 |
issn | 0018-9200 1558-173X |
language | eng |
recordid | cdi_proquest_miscellaneous_28146561 |
source | IEEE |
subjects | Batteries Circuit testing CMOS technology Electronic equipment Low voltage MOSFET circuits Operational amplifiers Random access memory Thin film transistors Threshold voltage |
title | A 1-V TFT-load SRAM using a two-step word-voltage method |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T10%3A17%3A57IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%201-V%20TFT-load%20SRAM%20using%20a%20two-step%20word-voltage%20method&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Ishibashi,%20K.&rft.date=1992-11-01&rft.volume=27&rft.issue=11&rft.spage=1519&rft.epage=1524&rft.pages=1519-1524&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.165331&rft_dat=%3Cproquest_RIE%3E28146561%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=28146561&rft_id=info:pmid/&rft_ieee_id=165331&rfr_iscdi=true |