A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier

A 9-ns 16-Mb CMOS SRAM with offset-compensated current sense amplifier

A 9-ns 16-Mb CMOS SRAM has been developed using a 0.35- mu m CMOS process, The current-mode fully nonequalized data path has been realized in a CMOS SRAM for the first time by using a stabilized feedback current-sense amplifier (SFCA) that provides a small input resistance and an offset compensation...

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Veröffentlicht in:IEEE journal of solid-state circuits 1993-11, Vol.28 (11), p.1119-1124
Hauptverfasser: Seno, K., Knorpp, K., Shu, L.-L., Teshima, N., Kihara, H., Sato, H., Miyaji, F., Takeda, M., Sasaki, M., Tomo, Y., Chuang, P.T., Kobayashi, K.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
Circuit testing
CMOS process
Electronics
Exact sciences and technology
Feedback
Integrated circuits
Integrated circuits by function (including memories and processors)
Large-scale systems
MOS devices
Pulse amplifiers
Pulse circuits
Random access memory
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Timing
Voltage
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Zusammenfassung:A 9-ns 16-Mb CMOS SRAM has been developed using a 0.35- mu m CMOS process, The current-mode fully nonequalized data path has been realized in a CMOS SRAM for the first time by using a stabilized feedback current-sense amplifier (SFCA) that provides a small input resistance and an offset compensation effect. To reduce the test time, a bit-line wired-OR parallel test circuit has been implemented.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.245591