A 10 b 50 MHz pipelined CMOS A/D converter with S/H
A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital e...
Gespeichert in:
Veröffentlicht in: | IEEE journal of solid-state circuits 1993-03, Vol.28 (3), p.292-300 |
---|---|
Hauptverfasser: | , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 300 |
---|---|
container_issue | 3 |
container_start_page | 292 |
container_title | IEEE journal of solid-state circuits |
container_volume | 28 |
creator | Yotsuyanagi, M. Etoh, T. Hirata, K. |
description | A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 mu m CMOS technology.< > |
doi_str_mv | 10.1109/4.209996 |
format | Article |
fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28125445</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>209996</ieee_id><sourcerecordid>25946392</sourcerecordid><originalsourceid>FETCH-LOGICAL-c335t-a76c637c5304946062c11639b7a6876a17cee64af129b099fd2d402c039d7f1f3</originalsourceid><addsrcrecordid>eNqFkE1Lw0AQhhdRsFbBs6c9iHhJO7Of2WOpHxVaeqiCt7DdbDCSJnE3VfTXm9Li1dPwMg_PDC8hlwgjRDBjMWJgjFFHZIBSpglq_npMBgCYJoYBnJKzGN_7KESKA8InFIGuqQS6mP3Qtmx9VdY-p9PFckUn4zvqmvrTh84H-lV2b3Q1np2Tk8JW0V8c5pC8PNw_T2fJfPn4NJ3ME8e57BKrlVNcO8lBGKFAMYeouFlrq1KtLGrnvRK2QGbW_c9FznIBzAE3uS6w4ENys_e2ofnY-thlmzI6X1W29s02ZixFJoWQ_4Oyv88N68HbPehCE2PwRdaGcmPDd4aQ7erLRLavr0evD04bna2KYGtXxj9eKKMl7IxXe6z03v9tD45fhaZxVQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>25946392</pqid></control><display><type>article</type><title>A 10 b 50 MHz pipelined CMOS A/D converter with S/H</title><source>IEEE Electronic Library (IEL)</source><creator>Yotsuyanagi, M. ; Etoh, T. ; Hirata, K.</creator><creatorcontrib>Yotsuyanagi, M. ; Etoh, T. ; Hirata, K.</creatorcontrib><description>A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 mu m CMOS technology.< ></description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.209996</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Analog-digital conversion ; Applied sciences ; Circuit properties ; CMOS analog integrated circuits ; CMOS technology ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; HDTV ; Operational amplifiers ; Sampling methods ; Signal convertors ; Signal resolution ; Video signal processing</subject><ispartof>IEEE journal of solid-state circuits, 1993-03, Vol.28 (3), p.292-300</ispartof><rights>1993 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c335t-a76c637c5304946062c11639b7a6876a17cee64af129b099fd2d402c039d7f1f3</citedby><cites>FETCH-LOGICAL-c335t-a76c637c5304946062c11639b7a6876a17cee64af129b099fd2d402c039d7f1f3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/209996$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,796,23930,23931,25140,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/209996$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=4697502$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Yotsuyanagi, M.</creatorcontrib><creatorcontrib>Etoh, T.</creatorcontrib><creatorcontrib>Hirata, K.</creatorcontrib><title>A 10 b 50 MHz pipelined CMOS A/D converter with S/H</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 mu m CMOS technology.< ></description><subject>Analog-digital conversion</subject><subject>Applied sciences</subject><subject>Circuit properties</subject><subject>CMOS analog integrated circuits</subject><subject>CMOS technology</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>HDTV</subject><subject>Operational amplifiers</subject><subject>Sampling methods</subject><subject>Signal convertors</subject><subject>Signal resolution</subject><subject>Video signal processing</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNqFkE1Lw0AQhhdRsFbBs6c9iHhJO7Of2WOpHxVaeqiCt7DdbDCSJnE3VfTXm9Li1dPwMg_PDC8hlwgjRDBjMWJgjFFHZIBSpglq_npMBgCYJoYBnJKzGN_7KESKA8InFIGuqQS6mP3Qtmx9VdY-p9PFckUn4zvqmvrTh84H-lV2b3Q1np2Tk8JW0V8c5pC8PNw_T2fJfPn4NJ3ME8e57BKrlVNcO8lBGKFAMYeouFlrq1KtLGrnvRK2QGbW_c9FznIBzAE3uS6w4ENys_e2ofnY-thlmzI6X1W29s02ZixFJoWQ_4Oyv88N68HbPehCE2PwRdaGcmPDd4aQ7erLRLavr0evD04bna2KYGtXxj9eKKMl7IxXe6z03v9tD45fhaZxVQ</recordid><startdate>19930301</startdate><enddate>19930301</enddate><creator>Yotsuyanagi, M.</creator><creator>Etoh, T.</creator><creator>Hirata, K.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>7U5</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19930301</creationdate><title>A 10 b 50 MHz pipelined CMOS A/D converter with S/H</title><author>Yotsuyanagi, M. ; Etoh, T. ; Hirata, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c335t-a76c637c5304946062c11639b7a6876a17cee64af129b099fd2d402c039d7f1f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Analog-digital conversion</topic><topic>Applied sciences</topic><topic>Circuit properties</topic><topic>CMOS analog integrated circuits</topic><topic>CMOS technology</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>HDTV</topic><topic>Operational amplifiers</topic><topic>Sampling methods</topic><topic>Signal convertors</topic><topic>Signal resolution</topic><topic>Video signal processing</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Yotsuyanagi, M.</creatorcontrib><creatorcontrib>Etoh, T.</creatorcontrib><creatorcontrib>Hirata, K.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Yotsuyanagi, M.</au><au>Etoh, T.</au><au>Hirata, K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A 10 b 50 MHz pipelined CMOS A/D converter with S/H</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1993-03-01</date><risdate>1993</risdate><volume>28</volume><issue>3</issue><spage>292</spage><epage>300</epage><pages>292-300</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 mu m CMOS technology.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/4.209996</doi><tpages>9</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0018-9200 |
ispartof | IEEE journal of solid-state circuits, 1993-03, Vol.28 (3), p.292-300 |
issn | 0018-9200 1558-173X |
language | eng |
recordid | cdi_proquest_miscellaneous_28125445 |
source | IEEE Electronic Library (IEL) |
subjects | Analog-digital conversion Applied sciences Circuit properties CMOS analog integrated circuits CMOS technology Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology HDTV Operational amplifiers Sampling methods Signal convertors Signal resolution Video signal processing |
title | A 10 b 50 MHz pipelined CMOS A/D converter with S/H |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-30T21%3A03%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%2010%20b%2050%20MHz%20pipelined%20CMOS%20A/D%20converter%20with%20S/H&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Yotsuyanagi,%20M.&rft.date=1993-03-01&rft.volume=28&rft.issue=3&rft.spage=292&rft.epage=300&rft.pages=292-300&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.209996&rft_dat=%3Cproquest_RIE%3E25946392%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=25946392&rft_id=info:pmid/&rft_ieee_id=209996&rfr_iscdi=true |