A 10 b 50 MHz pipelined CMOS A/D converter with S/H
A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital e...
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Veröffentlicht in: | IEEE journal of solid-state circuits 1993-03, Vol.28 (3), p.292-300 |
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Format: | Artikel |
Sprache: | eng |
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Zusammenfassung: | A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 mu m CMOS technology.< > |
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ISSN: | 0018-9200 1558-173X |
DOI: | 10.1109/4.209996 |