Structural optimization of SUTBDG devices for low-power applications

In this paper, we investigate the impact of physical structure on the performance of symmetric ultrathin body double-gate devices for low-operating-power (LOP) applications. Devices with regular raised source/drain (S/D) structures have optimal spacer thicknesses governed by a tradeoff between fringing capacitance and series resistance. Expanded S/D structures improve on regular raised S/D structures by slowing down the increases in both fringing capacitance with gate height and series resistance with spacer thickness. The cost is more chip area and process complexity. Pure high-/spl kappa/ gate dielectrics raise the off-state current (I/sub OFF/) due to the fringing field-induced barrier lowering effect. Suppressing the I/sub OFF/ increase requires either a significant reduction in equivalent oxide thickness or a significant shift in gate work function. If the gate work function is tuned to maintain a fixed I/sub OFF/, devices with less abrupt S/D-channel junctions suffer a drive current (I/sub ON/) degradation, and devices with weakly coupling S/D and relatively thick bodies gain improvements in I/sub ON/. The I/sub ON/ of a device with metal S/D is significantly lower than required for LOP applications, if the S/D Schottky barrier height (SBH) is over 200 meV. We also briefly discuss the impact of mobility degradation on this structural optimization.