Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits

We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, w...

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Veröffentlicht in:IEEE transactions on electron devices 2005-11, Vol.52 (11), p.2395-2403
Hauptverfasser: Akturk, A., Goldsman, N., Metze, G.
Format: Artikel
Sprache:eng
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Zusammenfassung:We present a new method for finding the temperature profile of vertically stacked three-dimensional (3-D) digital integrated circuits (ICs). Using our model, we achieve spatial thermal resolution at the desired circuit level, which can be as small as a single MOSFET. To resolve heating of 3-D ICs, we solve nonisothermal device equations self-consistently with lumped heat flow equations for the entire 3-D IC. Our methodology accounts for operational variations due to technology nodes (hardware: device), chip floor plans (hardware: layout), operating speed (hardware: clock frequency), and running applications (software). To model hardware, we first decide on an appropriate device configuration. We then calculate elements of the lumped thermal network using the 3-D IC layout. To include software, chip floor plan, and duty cycle-related performance variations, we employ a statistical Monte Carlo type algorithm. In this paper, we investigate performance of vertically stacked 3-D ICs, with each layer modeled after a Pentium III. Our calculated results show that layers within the stacked 3-D ICs, especially the ones in the middle, may greatly suffer from thermal heating.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2005.857187