The optimization of on-wafer shield-based test fixture layout

The effect of layout design on shield-based test fixture parasitic components is studied in this paper. As a result, guidelines for shield-based test fixture layout design are given. The novel test fixture layout details studied in this paper are a slotted ground plane with different slot orientation, the use of ground-bar extensions in a ground-shielded test fixture, and the upgrade of a ground-shielded test fixture to a fully shielded structure with a common ground. It was found that a slotted ground plane does not increase the ground lead impedance significantly. Thus, successful ground-shielded test fixture processing can be ensured by obeying process stress release design rules. Furthermore, the additional ground bar extensions had a negligible effect on reducing the ground-shielded test fixture ground lead impedance. However, upgrading the ground-shielded test fixture structure to fully shielded reduced the ground lead impedance. Therefore, fully shielded test fixtures are proposed for use with two-port cascade-based deembedding methods, which commonly are incapable of taking into account ground lead parasitic components.