Pixel noise suppression via SoC management of tapered reset in a 1920x1080 CMOS image sensor

Correlated double sampling is widely used in imaging arrays to eliminate noise generated when a CCD's sense capacitance or a CMOS sensor's photodiode is reset after signal integration and readout. Instead, we suppress photodiode kTC noise using a SoC implementation for progressive reset; supporting SoC components include a feedback amplifier having elements distributed amongst the pixel and column buffer, a tapered reset clock waveform, and reset timing generator. The reset method does not swell pixel area, compel processing of the correlated reset and signal values, or require additional memory. Theoretical analysis is presented along with experimental results. Integrated in a 1920 by 1080 imager having 5 mum by 5 mum pixels in 0.25-mum CMOS, measured random noise for 5.5-fF detector capacitance is /spl sim/8 e- to 225 MHz video rate with image lag < 0.12%. Random noise of /spl sim/30 e- is otherwise predicted and achieved using conventional reset. Sensor S/N ratio with progressive readout is /spl ges/52 dB at 60 Hz and 72 Hz frame rate.