Integration of high-performance transistors, high-density SRAMs, and 10-level copper interconnects into a 90 nm CMOS technology
This paper presents a 40 nm-gate-length transistor, an ultra-high-density 6T SRAM cell, 10-level Cu interconnects, and very-low-k (VLK) dielectrics for high-performance microprocessor applications. The key process features are 1) 193 nm lithography with a phase shift mask (PSM) and optical proximity...
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| Veröffentlicht in: | Fujitsu scientific & technical journal 2003-01, Vol.39 (1), p.23-31 |
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| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Online-Zugang: | Volltext |
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