Integration of high-performance transistors, high-density SRAMs, and 10-level copper interconnects into a 90 nm CMOS technology

This paper presents a 40 nm-gate-length transistor, an ultra-high-density 6T SRAM cell, 10-level Cu interconnects, and very-low-k (VLK) dielectrics for high-performance microprocessor applications. The key process features are 1) 193 nm lithography with a phase shift mask (PSM) and optical proximity correction (OPC) that enables us to fabricate a 40 nm-long gate and a sub-1 *mm2 SRAM cell, 2) a unique transistor feature called a sidewall-notched gate that enables optimal pocket implant placement and suppresses variations of the notch width much better than a poly-notched gate structure, 3) a 1.1 nm-thick nitrided oxide to achieve a high drive current and a reduced thermal budget to suppress boron penetration, and 4) an SiC-capped Cu/SiLK structure in 0.28 *mm-pitch Metal 1-4 layers that realizes a keff of 3.0.