Gate/drain bias-induced degradation effects in TFTs fabricated in unhydrogenated SPC polycrystalline silicon films

The behavior of the parameters of n-channel thin film transistors (TFTs) in unhydrogenated solid phase crystallized polysilicon films under gate and drain direct-current bias stresses was investigated. The density of states in these films was evaluated using ultraviolet–visible spectroscopy and a larger density of localized states below the bottom of the conduction band was correlated with poorer electrical parameters. The TFT threshold voltage exhibited an initial negative shift attributed to hole trapping and turnaround to positive shift under V GS stress, attributed to electron trapping in the oxide and at stress-induced interface states, with logarithmic stressing time dependence. The subthreshold slope and the electron mobility also exhibited logarithmic degradation. Stress-induced trap creation at the interface and in the polysilicon active layer was inferred as the main cause of these shifts. When a V DS stress is combined with the V GS stress bias the V th turnaround is suppressed and parameter degradation is enhanced, indicating an increase in stress-induced trap creation and electron trapping, in correlation with the increase of stressing current I DS.