A fast task-to-processor assignment heuristic for real-time multiprocessor DSP applications

The optimal assignment of the tasks to the processors to minimize total delay in a multiprocessor digital signal processing (DSP) architecture is extremely difficult, particularly for systems of many (e.g. 100) tasks. Two factors especially complicate the problem: (1) the multiprocessor architecture affects the inter-processor communication times, and (2) the specific assignment of tasks to processors affects the inter-task communication times. We develop a fast heuristic for assigning tasks to processors. There are two main ingredients in our method: (i) the choice of a useful general-purpose multiprocessor architecture for DSP applications, and (ii) an adaptive list-ordering heuristic which takes advantage of knowledge of the inter-processor communication characteristics of the chosen architecture. Examples are given, including comparisons to exact branch-and-bound methods, and a large sonar example. Scope and purpose General digital signal processing system architectures consist of an arrangement of signal processing units connected by communication links. The tasks to be carried out by the signal processing units are specified via a task graph similar to a PERT diagram. The challenge is to assign the tasks in the task graph to the signal processing units in the architecture in an optimal manner. In this paper, we are interested in task-to-processor assignments that minimize the total delay, which is the lag between the first appearance of a signal at the input port and the production of a processed signal at the output port. The assignment process is complicated by the need to consider the inter-task communication delays, which are themselves greatly affected by the assignment. The task-to-processor assignment problem is NP-complete, hence heuristics must be used. We develop a fast and effective heuristic for a specific general-purpose digital signal processing architecture.