Self-aligned GaAs p-channel enhancement mode MOS heterostructure field-effect transistor

Self-aligned GaAs p-channel enhancement mode MOS heterostructure field-effect transistor

Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga 2 O 3 gate oxide, an undoped Al/sub 0.75/Ga/sub 0.25/As spacer layer, and undoped In/sub 0.2/Ga/sub 0.8/As as channel layer. Th...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE electron device letters 2002-09, Vol.23 (9), p.508-510
Hauptverfasser: Passlack, M., Abrokwah, J.K., Droopad, R., Zhiyi Yu, Overgaard, C., Sang In Yi, Hale, M., Sexton, J., Kummel, A.C.
Format: Artikel
Sprache:eng
Schlagworte:
Devices
Epitaxial layers
Gallium arsenide
Gallium arsenides
Gates
HEMTs
Heterojunctions
Heterostructures
Indium
Metal oxide semiconductors
MODFETs
MOS devices
MOSFETs
Semiconductor device modeling
Semiconductor devices
Transconductance
Transistors
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga 2 O 3 gate oxide, an undoped Al/sub 0.75/Ga/sub 0.25/As spacer layer, and undoped In/sub 0.2/Ga/sub 0.8/As as channel layer. The p-channel devices with a gate length of 0.6 μm exhibit a maximum DC transconductance g/sub m/ of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality.
ISSN:0741-3106
1558-0563
DOI:10.1109/LED.2002.802591