High-speed sense circuit techniques for a 1-mbit BiCMOS cache SRAM
This paper describes a high‐speed and low‐power 1‐Mbit BiCMOS cache SRAM sense circuit fabricated using a 0.5‐μm BiCMOS process technology. By using the quasi‐6 module structure, switching between 18‐ and 36‐bit output can be carried out without access delay. Because of the development of a sense ci...
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| Veröffentlicht in: | Electronics & communications in Japan. Part 2, Electronics Electronics, 1998-08, Vol.81 (8), p.55-63 |
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| container_end_page | 63 |
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| container_issue | 8 |
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| container_title | Electronics & communications in Japan. Part 2, Electronics |
| container_volume | 81 |
| creator | Emori, Akihiko Suzuki, Kunihiko Yukutake, Seigoh Ookuma, Sadayuki Mitumoto, Kinya Akioka, Takashi Iwamura, Masahiro Akiyama, Noboru |
| description | This paper describes a high‐speed and low‐power 1‐Mbit BiCMOS cache SRAM sense circuit fabricated using a 0.5‐μm BiCMOS process technology. By using the quasi‐6 module structure, switching between 18‐ and 36‐bit output can be carried out without access delay. Because of the development of a sense circuit with a low‐amplitude current amplifier and equalization/write‐recovery circuit, the sense delay is 0.8 ns, which is 50% faster than the conventional common collector configuration. Using this new technique, a 1‐Mbit BiCMOS cache SRAM for 4.5‐ns cycle operation was fabricated. © 1998 Scripta Technica, Electron Comm Jpn Pt 2, 81(8): 55–63, 1998 |
| doi_str_mv | 10.1002/(SICI)1520-6432(199808)81:8<55::AID-ECJB8>3.0.CO;2-0 |
| format | Article |
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Part 2, Electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Emori, Akihiko</au><au>Suzuki, Kunihiko</au><au>Yukutake, Seigoh</au><au>Ookuma, Sadayuki</au><au>Mitumoto, Kinya</au><au>Akioka, Takashi</au><au>Iwamura, Masahiro</au><au>Akiyama, Noboru</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>High-speed sense circuit techniques for a 1-mbit BiCMOS cache SRAM</atitle><jtitle>Electronics & communications in Japan. Part 2, Electronics</jtitle><addtitle>Electron. Comm. Jpn. Pt. II</addtitle><date>1998-08</date><risdate>1998</risdate><volume>81</volume><issue>8</issue><spage>55</spage><epage>63</epage><pages>55-63</pages><issn>8756-663X</issn><eissn>1520-6432</eissn><abstract>This paper describes a high‐speed and low‐power 1‐Mbit BiCMOS cache SRAM sense circuit fabricated using a 0.5‐μm BiCMOS process technology. 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| identifier | ISSN: 8756-663X |
| ispartof | Electronics & communications in Japan. Part 2, Electronics, 1998-08, Vol.81 (8), p.55-63 |
| issn | 8756-663X 1520-6432 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_27531199 |
| source | Wiley Online Library Journals Frontfile Complete |
| subjects | BiCMOS cache memory module sense amplifier SRAM write-recovery |
| title | High-speed sense circuit techniques for a 1-mbit BiCMOS cache SRAM |
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