High-speed sense circuit techniques for a 1-mbit BiCMOS cache SRAM

This paper describes a high‐speed and low‐power 1‐Mbit BiCMOS cache SRAM sense circuit fabricated using a 0.5‐μm BiCMOS process technology. By using the quasi‐6 module structure, switching between 18‐ and 36‐bit output can be carried out without access delay. Because of the development of a sense circuit with a low‐amplitude current amplifier and equalization/write‐recovery circuit, the sense delay is 0.8 ns, which is 50% faster than the conventional common collector configuration. Using this new technique, a 1‐Mbit BiCMOS cache SRAM for 4.5‐ns cycle operation was fabricated. © 1998 Scripta Technica, Electron Comm Jpn Pt 2, 81(8): 55–63, 1998