ABR switch mechanisms: design issues and performance evaluation

Considerable protocol development efforts in recent ATM Forum activities have been centered on the traffic management of available bit rate (ABR) service. The goal is to efficiently manage the leftover network bandwidth and fairly distribute it among contending ABR virtual connections (VC) so that communication links can be optimally utilized. A rate-based flow control mechanism has been adopted for that purpose. While the ATM Forum Traffic Management Specification Version 4.0 document gives a complete description of the end system behavior, it gives only a high level description of the switch or intermediate network nodes, leaving the details of their behavior vendor implementation dependent. This paper is concerned with the variety of ABR switch mechanisms available for implementation with the current end system definition. The various switch mechanisms can be broadly classified in two categories depending on the type of feedback information provided to the end system. The feedback mechanism is either binary involving setting the EFCI bit in the data cell header or explicit rate in which case the switch has to calculate a target rate and send it back to the source through an RM cell. Also within each category, different subgroups are formed based on the type of queuing involved (for example per port queuing, per VC accounting, per VC queuing) and the congestion declaration criteria adopted (for example queue thresholding, queue derivative, load monitoring). Our goal is to provide an overview of the various switch mechanisms available and discuss their performance characteristics accordingly. The performance metrics used include queue length, source flow-controlled cell rate dynamics, fairness of bandwidth allocation in the steady state and ramp-up time in the network transient state. Simulations of the different switch algorithms' dynamics for network configurations and scenarios of interest are presented.