Downsizing gold wires to submicron range: a self-planarized gold metallization process by selective electroplating for silicon LSI applications

A self-planarized Au metallization process by electrolytic plating has been developed for metal interconnection in the submicron range. Gold wires with depth-to-width aspect ratio > 2 were fabricated in a buried structure within the dielectric spacer. By etching of Au and oxidizing the surface of TiW in the field, the Au wires can be selectively formed and planarized within the dielectrics. This process can provide desired properties of conductor structures for silicon LSI applications. More important, the process is economically viable due to its simplicity and low cost in capital equipment purchase, maintenance and operation.