A CMOS analog timing recovery circuit for PRML detectors

A fully integrated analog timing recovery circuit for partial-response maximum-likelihood (PRML) detectors for digital magnetic storage is described. The circuit uses a decision-directed minimum mean-squared error (MMSE) algorithm and achieves phase acquisition within 100-bit periods at a maximum speed of 180 Mb/s. It dissipates 76 mW from a single 3.3-V supply and has an active die area of 1.8 mm/sup 2/ in a 1.2-/spl mu/m CMOS process. At 180 Mb/s, the rms clock fitter is 15 ps and peak-to-peak jitter is 97 ps. The test results demonstrate the feasibility of an analog CMOS implementation of decision-directed MMSE timing recovery for PRML detectors.