IC test structures for multilayer interconnect stress determination

IC test structures for multilayer interconnect stress determination

A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measureme...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE electron device letters 2000-01, Vol.21 (1), p.12-14
Hauptverfasser: Smee, S.A., Gaitan, M., Novotny, D.B., Joshi, Y., Blackburn, D.L.
Format: Artikel
Sprache:eng
Schlagworte:
Arrays
Circuit testing
CMOS
CMOS process
Dielectric measurements
Integrated circuit interconnections
Integrated circuit testing
Integrated circuits
Mathematical analysis
Micromechanical devices
Multilayers
Nonhomogeneous media
Strain measurement
Stress measurement
Stresses
Thermal stresses
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures. Stress values, calculated from constitutive relations, are in good agreement with published results.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.817437