Concentrator circuit with multiple priority levels

Concentrator circuit with multiple priority levels

The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 mu m CMOS technology.

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Veröffentlicht in:Electronics letters 2000-03, Vol.36 (6), p.500-501
Hauptverfasser: Krishnamoorthy, A.V., Chiou, Lih-yih, Rozier, R.G., Kibar, O.
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container_end_page 501
container_issue 6
container_start_page 500
container_title Electronics letters
container_volume 36
creator Krishnamoorthy, A.V.
Chiou, Lih-yih
Rozier, R.G.
Kibar, O.
description The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 mu m CMOS technology.
doi_str_mv 10.1049/el:20000287
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title Concentrator circuit with multiple priority levels
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