Concentrator circuit with multiple priority levels

Concentrator circuit with multiple priority levels

The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 mu m CMOS technology.

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Electronics letters 2000-03, Vol.36 (6), p.500-501
Hauptverfasser: Krishnamoorthy, A.V., Chiou, Lih-yih, Rozier, R.G., Kibar, O.
Format: Artikel
Sprache:eng
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:The architecture is presented of a memory-less CMOS packet concentrator that carries out dynamic statistical multiplexing of data from N inputs to L outputs with multiple priority levels. Results are presented from a 16-channel test chip built using 0.5 mu m CMOS technology.
ISSN:0013-5194
1350-911X
DOI:10.1049/el:20000287