A Kernel‐Based Partitioning Algorithm for Low‐Power, Low‐Area Overhead Circuit Design Using Don't‐Care Sets

This letter proposes an efficient kernel‐based partitioning algorithm for reducing area and power dissipation in combinational circuit designs using don't‐care sets. The proposed algorithm decreases power dissipation by partitioning a given circuit using a kernel extracted from the logic. The proposed algorithm also reduces the area overhead by minimizing duplicated gates in the partitioned sub‐circuits. The partitioned subcircuits are further optimized utilizing observability don't‐care sets. Experimental results for the MCNC benchmarks show that the proposed algorithm synthesizes circuits that on the average consume 22.5% less power and have 12.7% less area than circuits generated by previous algorithms based on a precomputation scheme.