Fabrication Technology and Device Performance of Sub-50-nm-Gate InP-Based High Electron Mobility Transistors

Authors fabricated sub-50-nm-gate InAlAs/InGaAs high electron mobility transistors (HEMTs) lattice-matched to InP substrates. The two-step-recessed gate technology and low-temperature process, with all steps taking place below 300 C, allowed authors to fabricate sub-50-nm-gate HEMTs that had high le...

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Veröffentlicht in:	Japanese Journal of Applied Physics 2002, Vol.41 (Part 1, No. 2B), p.1094-1098
Hauptverfasser:	Endoh, Akira, Yamashita, Yoshimi, Shinohara, Keisuke, Higashiwaki, Masataka, Hikosaka, Kohki, Mimura, Takashi, Hiyamizu, Satoshi, Matsui, Toshiaki
Format:	Artikel
Sprache:	eng
Online-Zugang:	Volltext
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