A review of narrow-channel effects for STI MOSFET's: A difference between surface- and buried-channel cases

The shallow trench isolation (STI) is one of the key technologies for VLSI. The threshold voltage V th for surface-channel STI MOSFET's becomes lower with decreasing channel width W, which is called the inverse narrow-channel effect (INCE). Also, there is a hump in the subthreshold characterist...

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Veröffentlicht in:Solid-state electronics 1999-11, Vol.43 (11), p.2061-2066
Hauptverfasser: Shigyo, Naoyuki, Hiraoka, Takayuki
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Hiraoka, Takayuki
description The shallow trench isolation (STI) is one of the key technologies for VLSI. The threshold voltage V th for surface-channel STI MOSFET's becomes lower with decreasing channel width W, which is called the inverse narrow-channel effect (INCE). Also, there is a hump in the subthreshold characteristic. On the contrary, buried-channel STI MOSFET's reveal a conventional narrow-channel effect. Also, there is no hump in the subthreshold characteristic. This paper reviews above phenomena with a consistent explanation for the surface- and buried-channel STI MOSFET's. Countermeasures for INCE are also discussed.
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fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_27107681</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0038110199001574</els_id><sourcerecordid>27107681</sourcerecordid><originalsourceid>FETCH-LOGICAL-c404t-bb353ccc35ac31c085cbfaf71ab795415b38cb7c17ff65fae5033e97777864a33</originalsourceid><addsrcrecordid>eNqFkE1PwzAMhiMEEmPwE5By4uNQSJamabmgaeJj0tAOG-codR0R6NqRtEz8e7INccUXW_LrR_JDyDlnN5zx7HbBmMgTHuerorhmjEuVpAdkwHNVJKOUyUMy-Isck5MQ3hljo4yzAfkYU49fDje0tbQx3rebBN5M02BN0VqELlDberpYTunLfPH4sLwMd3RMKxeXHhtAWmK3QWxo6L01gAk1TUXL3jus_lBgAoZTcmRNHfDstw_Ja-RNnpPZ_Gk6Gc8SSFnaJWUppAAAIQ0IDiyXUFpjFTelKmTKZSlyKBVwZW0mrUHJhMBCxcqz1AgxJBd77tq3nz2GTq9cAKxr02DbBz1SnKks5zEo90HwbQgerV57tzL-W3Omt2r1Tq3eetNFoXdqdRrv7vd3GL-I8rwO4LYuKuejMV217h_CD2cMf_Q</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>27107681</pqid></control><display><type>article</type><title>A review of narrow-channel effects for STI MOSFET's: A difference between surface- and buried-channel cases</title><source>ScienceDirect Journals (5 years ago - present)</source><creator>Shigyo, Naoyuki ; Hiraoka, Takayuki</creator><creatorcontrib>Shigyo, Naoyuki ; Hiraoka, Takayuki</creatorcontrib><description>The shallow trench isolation (STI) is one of the key technologies for VLSI. The threshold voltage V th for surface-channel STI MOSFET's becomes lower with decreasing channel width W, which is called the inverse narrow-channel effect (INCE). Also, there is a hump in the subthreshold characteristic. On the contrary, buried-channel STI MOSFET's reveal a conventional narrow-channel effect. Also, there is no hump in the subthreshold characteristic. This paper reviews above phenomena with a consistent explanation for the surface- and buried-channel STI MOSFET's. Countermeasures for INCE are also discussed.</description><identifier>ISSN: 0038-1101</identifier><identifier>EISSN: 1879-2405</identifier><identifier>DOI: 10.1016/S0038-1101(99)00157-4</identifier><language>eng</language><publisher>Elsevier Ltd</publisher><ispartof>Solid-state electronics, 1999-11, Vol.43 (11), p.2061-2066</ispartof><rights>1999 Elsevier Science Ltd</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c404t-bb353ccc35ac31c085cbfaf71ab795415b38cb7c17ff65fae5033e97777864a33</citedby><cites>FETCH-LOGICAL-c404t-bb353ccc35ac31c085cbfaf71ab795415b38cb7c17ff65fae5033e97777864a33</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://dx.doi.org/10.1016/S0038-1101(99)00157-4$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,780,784,3550,27924,27925,45995</link.rule.ids></links><search><creatorcontrib>Shigyo, Naoyuki</creatorcontrib><creatorcontrib>Hiraoka, Takayuki</creatorcontrib><title>A review of narrow-channel effects for STI MOSFET's: A difference between surface- and buried-channel cases</title><title>Solid-state electronics</title><description>The shallow trench isolation (STI) is one of the key technologies for VLSI. The threshold voltage V th for surface-channel STI MOSFET's becomes lower with decreasing channel width W, which is called the inverse narrow-channel effect (INCE). Also, there is a hump in the subthreshold characteristic. On the contrary, buried-channel STI MOSFET's reveal a conventional narrow-channel effect. Also, there is no hump in the subthreshold characteristic. This paper reviews above phenomena with a consistent explanation for the surface- and buried-channel STI MOSFET's. Countermeasures for INCE are also discussed.</description><issn>0038-1101</issn><issn>1879-2405</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1999</creationdate><recordtype>article</recordtype><recordid>eNqFkE1PwzAMhiMEEmPwE5By4uNQSJamabmgaeJj0tAOG-codR0R6NqRtEz8e7INccUXW_LrR_JDyDlnN5zx7HbBmMgTHuerorhmjEuVpAdkwHNVJKOUyUMy-Isck5MQ3hljo4yzAfkYU49fDje0tbQx3rebBN5M02BN0VqELlDberpYTunLfPH4sLwMd3RMKxeXHhtAWmK3QWxo6L01gAk1TUXL3jus_lBgAoZTcmRNHfDstw_Ja-RNnpPZ_Gk6Gc8SSFnaJWUppAAAIQ0IDiyXUFpjFTelKmTKZSlyKBVwZW0mrUHJhMBCxcqz1AgxJBd77tq3nz2GTq9cAKxr02DbBz1SnKks5zEo90HwbQgerV57tzL-W3Omt2r1Tq3eetNFoXdqdRrv7vd3GL-I8rwO4LYuKuejMV217h_CD2cMf_Q</recordid><startdate>19991101</startdate><enddate>19991101</enddate><creator>Shigyo, Naoyuki</creator><creator>Hiraoka, Takayuki</creator><general>Elsevier Ltd</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19991101</creationdate><title>A review of narrow-channel effects for STI MOSFET's: A difference between surface- and buried-channel cases</title><author>Shigyo, Naoyuki ; Hiraoka, Takayuki</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c404t-bb353ccc35ac31c085cbfaf71ab795415b38cb7c17ff65fae5033e97777864a33</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1999</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Shigyo, Naoyuki</creatorcontrib><creatorcontrib>Hiraoka, Takayuki</creatorcontrib><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Solid-state electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Shigyo, Naoyuki</au><au>Hiraoka, Takayuki</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A review of narrow-channel effects for STI MOSFET's: A difference between surface- and buried-channel cases</atitle><jtitle>Solid-state electronics</jtitle><date>1999-11-01</date><risdate>1999</risdate><volume>43</volume><issue>11</issue><spage>2061</spage><epage>2066</epage><pages>2061-2066</pages><issn>0038-1101</issn><eissn>1879-2405</eissn><abstract>The shallow trench isolation (STI) is one of the key technologies for VLSI. The threshold voltage V th for surface-channel STI MOSFET's becomes lower with decreasing channel width W, which is called the inverse narrow-channel effect (INCE). Also, there is a hump in the subthreshold characteristic. On the contrary, buried-channel STI MOSFET's reveal a conventional narrow-channel effect. Also, there is no hump in the subthreshold characteristic. This paper reviews above phenomena with a consistent explanation for the surface- and buried-channel STI MOSFET's. Countermeasures for INCE are also discussed.</abstract><pub>Elsevier Ltd</pub><doi>10.1016/S0038-1101(99)00157-4</doi><tpages>6</tpages></addata></record>
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title A review of narrow-channel effects for STI MOSFET's: A difference between surface- and buried-channel cases
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T00%3A47%3A40IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20review%20of%20narrow-channel%20effects%20for%20STI%20MOSFET's:%20A%20difference%20between%20surface-%20and%20buried-channel%20cases&rft.jtitle=Solid-state%20electronics&rft.au=Shigyo,%20Naoyuki&rft.date=1999-11-01&rft.volume=43&rft.issue=11&rft.spage=2061&rft.epage=2066&rft.pages=2061-2066&rft.issn=0038-1101&rft.eissn=1879-2405&rft_id=info:doi/10.1016/S0038-1101(99)00157-4&rft_dat=%3Cproquest_cross%3E27107681%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=27107681&rft_id=info:pmid/&rft_els_id=S0038110199001574&rfr_iscdi=true