CHISEL flash EEPROM - Part I: Performance and scaling

In this work, we demonstrate the feasibility of using channel initiated secondary electron (CHISEL) programming in high-density flash memories containing fully scaled memory cells. We discuss programming performance, cell channel length scaling, endurance, and reliability of single cells and large arrays. In Part I of this work, we show successful CHISEL programming operation in fully scaled flash cells having channel lengths down to 0.22 mu m. Compared to conventional channel not electron (CHE) programming. CHISEL operation shows faster programming for identical drain bias, and lower power consumption for similar programming speed. The effect of channel length scaling on CHISEL operation and related device optimization is discussed using measurements and device simulation. Measurement on optimized floating gate contacted devices having channel length down to 0.14 mu m show good programming efficiency under CHISEL operation. The reliability and endurance of CHISEL operation in single cells and large arrays are discussed in Part II of this work.