Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors

A technique to extract trap states at the oxide-silicon interface and grain boundary has been developed for polycrystalline silicon thin-film transistors with large grains. From the capacitance–voltage characteristic, the oxide-silicon interface traps can be extracted. Potential and carrier density are also extracted. From the potential, carrier density, and current–voltage characteristic, the grain boundary traps can be extracted by considering the potential barrier at the grain boundary. Since these trap states are sequentially extracted, any shape of energy distribution of the trap states can be extracted. The correctness of this extraction technique is confirmed by comparison with two-dimensional device simulation.