A 48-16-MHz CMOS SC decimation filter

This paper presents a CMOS switched-capacitor decimation filter for prefiltering operations in video communications systems, reducing the complexity of continuous-time antialiasing filters and alleviating dynamic range requirements of analog-to-digital converters. As a consequence of the structure's low sensitivity to process variations, predicted by theory and verified in the laboratory by measurements on all samples of the same batch, it was possible to apply capacitor arrays having minimum feasible size units of 100 fF to implement the filter coefficients, leading to substantial savings in power consumption. Implemented in a standard 0.8-/spl mu/m CMOS process with poly-poly capacitors, the experimental device samples the incoming continuous-time analog signal at 48 MHz and presents a filtered sampled-data output at 16 MHz, with a measured pass-band deviation smaller than 0.22 dB up to the cutoff frequency of 3.6 MHz, output noise power spectrum of 1.1 nV/sub RMS///spl radic/(Hz) and a signal handling ability of 1.4 V/sub pp/, resulting in a dynamic range of 48 dB, meeting the usual specifications for video-frequency signal processing.